This invention is related to integrated circuit devices having memory functions and, in particular, to static random access memory (SRAM) devices.
From the invention of the integrated circuit in the late 1950's, circuit designs have been in constant development, particularly for integrated devices, in keeping with the developing semiconductor technologies. An early technology was bipolar technology which, compared to later integrated circuit technologies, occupied much space on a semiconductor substrate surface and required large amounts of electrical current with resulting high power consumption. Later field-effect technologies, particularly MOS (Metal-Oxide-Semiconductor) technology, used transistors which were much smaller than their bipolar counterparts with lower currents and consequently lower power consumption. CMOS (Complementary MOS) technology lowered currents and power consumption in an integrated circuit even further. Currently nearly all large-scale integrated circuits have turned to complementary metal oxide semiconductor (CMOS) technology.
Bipolar technology for semiconductor memory has been investigated over the years. But this research has typically focused upon the individual memory cell and has stopped at the conclusion that the memory cell could be part of an array. Further research and development of a bipolar memory cell array has been hampered by the longstanding belief that the CMOS memory cells occupied less space and consumed less power than any bipolar memory cell and that any bipolar memory cell array would necessarily be inferior to a CMOS array. Progress in recent years has relied upon relentless scaling in semiconductor processing technology, thus shrinking memory cell dimensions for greater circuit densities and higher operational speeds.
One integrated circuit implemented in CMOS technology is the SRAM, a circuit which employs bistable latching circuitry in its memory cells, enabling an SRAM memory cell to stay in a logic “1” or a logic “0” state as long as power is applied to the cell. Two cross-coupled inverters, each of which includes an active transistor and a complementary load transistor, and two select transistors, form the six-transistor CMOS SRAM cell which has been used for decades. Many integrated circuits in use today require a combination of CMOS logic circuits and on-chip high performance memories. Modern high performance processors and System-on-Chip (SoC) applications demands more on-chip memory to meet the performance and throughput requirements. For example, one integrated circuit can include 32 megabytes of CMOS SRAM as a cache memory on the chip. With a VDD of 0.9 volts and a leakage current of 25 nanoamperes per memory cell, such a circuit consumes 7 amperes just from the memory array, without considering the power consumption of the logic portion of the chip. In addition, as the size of such circuits shrink with continued scaling in process technology used to manufacture the circuits, the stability and power consumption of the memory cells have become one of the limiting factors in process cost and circuit complexity, making the designers of such chips reluctant to use the latest process technology.
The CMOS SRAM in such devices typically has an access time on the order of 200 picoseconds with a standard deviation of 30 picoseconds. Thus to obtain 6−σ sigma reliability an additional allowance of 6×30 picoseconds is necessary, resulting in a requirement to allow 380 picoseconds for access to the memory cells. The use of faster bipolar technology in such devices is typically limited to driver circuits in the SRAM memory, and even when used there, a more complicated bipolar CMOS (BiCMOS) fabrication process is used, requiring additional thermal cycles and making the fabrication of the MOS devices more difficult and expensive.
As semiconductor processes shrink down to nanometer generations, however, both leakage and active currents through MOS transistors are particularly susceptible to wide variations compared to the currents comparably sized bipolar transistors. Projections indicate that with increased packing densities and statistical deviations in electrical current the operation of future CMOS SRAM devices is problematical. It is desirable that an alternative approach be found.
The present invention provides for an SRAM memory cell that is based upon a thyristor, one form of bipolar technology and often represented by two coupled bipolar transistors. The memory cell is highly adaptable with many variations and the resulting SRAM integrated circuit can be designed for high-speed operation, or for lower speed operation if less power is required, or even for higher integration if a tightly packed SRAM integrated circuit is required. Furthermore, the SRAM memory cell can be manufactured with conventional CMOS technologies to avoid the development costs of a new technology.